In a power semiconductor device, it is known that the power semiconductor device has a structure in which a current detection element is provided on the same substrate so that the device is capable of being isolated in response to an overcurrent detection to protect the device (for example, Patent document 1). Patent document 1 describes a structure of a semiconductor device, such as an IGBT (Insulated Gate Bipolar Transistor), in which a current detection element for the semiconductor device is provided on the same substrate and a p-type region similar to a base region is formed under a current detection bonding pad for the current detection element.
Patent document 2 describes a power semiconductor device configured with a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and diodes; and, FIG. 1 and FIG. 2 in the document shows that at least one line of diodes is arranged in the periphery of a MOSFET cell region, i.e. in a region adjacent to a gate pad. When the MOSFET switches from ON state to OFF state, each of the diodes absorbs holes that are, when biased forward, injected to an N-type semiconductor layer in a drain side from a P-well and a P-base shown in FIG. 2 of the document. Therefore, when the MOSFET is switched from a forward bias to a backward bias, the structure described in the document can prevent a parasitic transistor shown in FIG. 3 of the document from turning ON.
FIG. 2 of the document shows that in the structure mentioned above, the P-base that is the P-well of the MOSFET is electrically connected to a source electrode through a back gate.